Modern electronic devices such as a notebook computer comprise a variety of memories to store information. Memory circuits include two major categories. One is volatile memories; the other is non-volatile memories. Volatile memories include random access memory (RAM), which can be further divided into two sub-categories, static random access memory (SRAM) and dynamic random access memory (DRAM). Both SRAM and DRAM are volatile because they will lose the information they store when they are not powered. On the other hand, non-volatile memories can keep data stored on them permanently unless non-volatile memories are exposed to an electrical charge. Non-volatile memories include a variety of sub-categories, such as electrically erasable programmable read-only memory (EEPROM) and flash memory.
SRAM cells may comprise different numbers of transistors. According to the total number of transistors in an SRAM cell, the SRAM cell may be referred to as a six-transistor (6-T) SRAM, an eight-transistor (8-T) SRAM, and the like. SRAM cells are arranged in rows and columns. An SRAM cell is selected during either a read operation or a write operation by selecting its row and column. The row and column to be selected are determined by a binary code. For example, a 64Kb memory chip may comprise a 16-bit binary code controlling the write and read operation. More particularly, the 16-bit binary code is split into two separate 8-bit binary codes for selecting a row and a column respectively. The 64Kb memory chip may further comprise a row decoder and a column decoder. In response to an 8-bit code, the row decoder is able to generate 28 outputs, which comes to 256 outputs. Likewise, the column decoder is able to generate another 28 outputs. By enabling an output from the row decoder and an output from the column decoder, an SRAM cell can be selected from a memory cell matrix having 256 rows and 256 columns.
In a read operation, the access time of detecting a logic state stored in a memory cell is a key performance index for a memory circuit. The major delay may result from bit line sensing due to the large capacitance resulting from a large number of memory cells coupled to a bit line. In order to reduce delay associated with bit line sensing, modern memory circuits may partition bit lines into two groups, namely local bit lines and global bit lines. As a result, a local bit line may perform a fast read operation because the capacitance of the local bit line is reduced in comparison to that of the bit line in a memory circuit without bit line partitioning.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.